1. Field of the Invention
The present invention relates to a method for fabricating an integrated circuit. More particularly, the present invention relates to a method for forming a borderless via in a semiconductor device.
2. Description of the Related Art
Before the development of techniques for forming deep sub-micron semiconductor devices, critical dimension (CD) of devices used to be quite large. Although there is some misalignment in a photolithographic process so that the vias are slightly offset, later-formed contacts can still land on the desired metal conductive lines. Operating characteristics of the device are affected very little by the misalignment.
FIG. 1 is a schematic, cross-sectional view showing an interconnect structure according to the prior art. As shown in FIG. 1, a plug 118 is formed on a metal conductive line 104. The plug 118 is a conductive structure in a via 114 formed in an inter-metal dielectric (IMD) layer 112. A structure between the metal conductive line 104 and a substrate 100 is another IMD layer or an interlayer dielectric layer 102.
Therefore, when techniques for fabricating deep sub-micron devices are employed, critical dimensions of devices shrink considerably. A very small misalignment of the via 114 or the plug 118 to the conductive line 104 often can have considerable effect on the operating characteristics of the devices. Thus, alignments of the via 114 and the plug 118 to the conductive line 104 become critical, especially when the desired dimension of the device exceeds or approaches the acceptable tolerance of the fabricating equipment. Hence, the conventional method is incapable of fabricating a via or a plug that lands exactly on the desired location according to deep-submicron device specification.
Therefore, innovative techniques for forming a borderless via or plug are required in order to fabricate a deep submicron device. In particular, the formation of interconnects between a large number of layers to form a multi-level interconnect (MLM) system depends very much on the capacity to form the high-quality borderless via or plug.
In addition, according to the prior art, an over-etching process is required in the fabrication of an interconnect structure. However, in the over-etching process, a metal conductive line is exposed, and the exposed metal conductive line reacts with an etching agent. The contact resistance Rc of the via is thus increased.